Optimized AES Implementation on Leon3

Authors

  • Ashish Mishra Department of Electrical and Electronics Engineering, BITS-Pilani, Pilani, Rajasthan, India
  • Sanal Kumar Department of Electrical and Electronics Engineering, BITS-Pilani, Pilani, Rajasthan, India
  • Jaldeep Vasavada Department of Electrical and Electronics Engineering, BITS-Pilani, Pilani, Rajasthan, India
  • Kota Solomon Raju Reconfigurable Computing Systems & Wireless Sensor Network Systems Lab, Digital System Group, CSIR-CEERI, Pilani, Rajasthan, India

DOI:

https://doi.org/10.37591/jovdtt.v5i1.1581

Abstract

This paper presents implementation of AES (Advanced Encryption Standard) on LEON3 which is a soft-core processor. We have used the AMBA (Advanced Microcontroller Bus Architecture) bus for interfacing our AES IP (Intellectual Property) core with Leon3 processor. AMBA bus is an in built open source bus which comes along with Leon3 processor. We have mainly analyzed parameters such as throughput, slice utilization and compared our model based with previous work. We have presented an optimized AES implementation and have tried to get maximum efficiency and tested the design on Atlys board.

Keywords: Xilinx, LEON3, simulator, AES, AMBA, field programmable gate arrays, Spartan-6

Cite this Article:
Mishra A, Kumar S, Vasavada J, Raju KS. Optimized AES Implementation on Leon3. Journal of VLSI Design Tools and Technology (JoVDTT). 2015; 5(1): 30–33p.

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Published

2019-02-13

Issue

Vol. 5 No. 1 (2015)

Section

Articles

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