Characterization of High Speed Phase Frequency Detector Circuit

Authors

  • Nilesh D. Patel Institute of Technology, Nirma University, Ahmedabad, Gujarat, India
  • Amisha P. Naik Institute of Technology, Nirma University, Ahmedabad, Gujarat, India

DOI:

https://doi.org/10.37591/jovdtt.v5i1.1585

Abstract

In this paper the performance of high speed phase frequency detector (PFD) is analysed. A high-speed PFD reduces the power consumption of traditional PFD to 0.423 nW at 1 GHz clock frequency and dead zone to 2 ps. It is suitable for low power applications. A PFD uses only 18 transistors. This PFD operates up to 1 GHz at 1.2 V supply voltage. The proposed architecture of the PFD has been implemented using 0.35μm CMOS technology and 90 nm CMOS technology.

Keywords: low power PFD, phase frequency detector, phase-locked loop, PLL

Cite this Article:
Nilesh D. Patel, Amisha P. Naik, Characterization of High Speed Phase Frequency Detector Circuit, Journal of VLSI Design Tools and Technology (JoVDTT).2015; 5(1): 51–58p.

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Published

2019-02-13

Issue

Vol. 5 No. 1 (2015)

Section

Articles

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