4-Bit Magnitude Comparator Design using Different Logic Styles

Authors

  • Vipul Mittal Department of Electrical Electronics and Communication Engineering (EECE), ITM University, Gurgaon, Haryana, India
  • Tanushree . Department of Electrical Electronics and Communication Engineering (EECE), ITM University, Gurgaon, Haryana, India
  • Madhulika Arora Department of Electrical Electronics and Communication Engineering (EECE), ITM University, Gurgaon, Haryana, India
  • Meenakshi Yadav Department of Electrical Electronics and Communication Engineering (EECE), ITM University, Gurgaon, Haryana, India
  • Sakshi Chaudhary Department of Electrical Electronics and Communication Engineering (EECE), ITM University, Gurgaon, Haryana, India

DOI:

https://doi.org/10.37591/jovdtt.v5i2.1596

Abstract

4-Bit Magnitude Comparator using various logic styles is explained here. Comparison is one of the common arithmetic operations that is used to determine which number is greater, equal to, or less. Every device from OP-AMP to ALU needs to perform comparison operations. At designing level, comparator can be designed by using different logic styles. Here, comparison is done for simple 4-Bit combinational comparator and cascaded comparator which we have designed and have calculated the power and delay for both the designs. Results for both the designs are presented in the form of simulations that is performed on Cadence virtuoso at 180 nm technology at different voltages.

Keywords: Comparator, arithmetic, virtuoso, cascaded, power, delay

Cite this Article

Vipul Mittal, Tanushree, Madhulika Arora, Meenakshi Yadav, Sakshi Chaudhary. 4-Bit Magnitude Comparator Design Using Different Logic Styles, Journal of VLSI Design Tools and Technology. 2015; 5 (2): 16–22p.

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Published

2019-02-15

Issue

Vol. 5 No. 2 (2015)

Section

Articles

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