A Novel Efficient VLSI Architecture for Matrix Multiplication using Compressor-based Multiplier

Authors

  • Kirti Sharma Dept. of Electronic and Communications, Hindustan College of Science & Technology, Mathura, U.P., India
  • Anushree . Dept. of Electronic and Communications, Hindustan College of Science & Technology, Mathura, U.P., India

DOI:

https://doi.org/10.37591/jovdtt.v5i2.1597

Abstract

Due to advancement of new technology in the field of VLSI, there is an increasing demand of high speed processor. Matrix multiplication is highly used in different types of computations. Speed of processor greatly depends on its multiplier (used in matrix multiplication) performance. Due to which high speed multiplier architecture become important. Several multiplication techniques have been developed to increase the efficiency of the multiplier. These techniques help in reducing the partial products and the methods of their addition but the principle behind multiplication remains same in all. In this paper, efficient VLSI architecture for matrix multiplication using different types of multipliers (i.e., Vedic multiplier and multiplier using compressor) is investigated.

Keywords: matrix multiplication (MM), Vedic mathematics, parallel to parallel input multiple output (PPI-MO), Urdhva Tiryakbhyam Sutra, 4:2 compressor

Cite this Article

Sharma K, Anushree. A Novel Efficient VLSI Architecture for Matrix Multiplication Using Compressor-Based Multiplier. Journal of VLSI Design Tools and Technology (JoVDTT). 2015; 5(2): 23–28p.


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Published

2019-02-15

Issue

Vol. 5 No. 2 (2015)

Section

Articles

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