Power-delay Product Optimal Design of Sequential Circuits Using Carbon Nanotubes

Abstract

This paper presents a power-aware high-performance design of ternary combinational and sequential circuits based on carbon nanotube field effect transistor (CNFET) using ternary logic. Carbon nanotube based field effect transistor (CNFET) are being studied extensively as a possible and promising choice for nanoscale integration and as successor to complementary metal oxide semiconductor (CMOS) devices. Ternary logic circuit has attracted substantial interest due to its simplicity, energy efficiency, and reduced interconnect as it has capability of increasing information content per unit area. The motive of present work is to propose a minimal power-delay product (PDP) circuits for ternary combinational and sequential circuits. Ternary combinational and sequential circuits are realized using ternary as well as combination of binary and ternary logic gates. Consequently, the geometry-dependent threshold voltage (V_th) of CNFET is used effectively while designing a ternary ALU (T-ALU) and subsequently a ternary SR latch using ternary as well as combination of binary and ternary logic gates. HSPICE simulations are employed for computing the PDP of ternary ALU using ternary logic and combination of binary and ternary logic is found to be 3:8598 fJoule, 0:10416 fJoule respectively. These examples illustrate that there is up to 97% reduction in PDP using combination of binary and ternary gates.

Keywords: Carbon nanotube field effect transistors, power delay product, ternary logic circuits, ternary ALU, ternary SR latch