Performance Analysis and Characterization of Shared Charge and Clocked-Latch based Comparator using 90-nm Technology

Authors

  • Vijay Savani Department of Electronics & Communication Engineering, Institute of Technology, Nirma University, Ahmedabad, India
  • N. M. Devashrayee

DOI:

https://doi.org/10.37591/jovdtt.v4i3.2933

Abstract

Paper describes the performance analysis, implementation and characterization of low-power and high-speed shared charge clocked-latch based comparator using 90-nm technology. There are two different topologies of the comparator viz. impedance dividing and differential current sensing comparators are combined to take the advantages and use their good features. The main focus of design is on improvement in speed by sharing charge and reduction in power dissipation. The topology is implemented in the 90-nm technology, obtained results are compared with the previous work at 180-nm technology. The implementation has been carried out using EDA tool of Mentor Graphic’s IC Station and simulation results are obtained using Eldo Spice.

 

Index Terms: Impedance dividing comparator, differential current sensing comparator, shared charge and clocked-latch based comparator, mentor graphics IC Station

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Published

2019-08-08

Issue

Vol. 4 No. 3 (2014)

Section

Articles

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