Detailed Study of Working and Applications of FinFET Technology and Its Adaptability in Current Era

Authors

  • manan sheth Electronics and Communication Department, Nirma University, India L. D. College of Engineering, India
  • shivang bakliwal
  • shival trivedi
  • dhaval shah

DOI:

https://doi.org/10.37591/jovdtt.v2i1-2-3.2958

Abstract

The CMOS technology is following Moore’s law since almost 25 years. The scaling of CMOS transistor has increased packaging density, speed and decreased power dissipation in the integrated circuits. However, CMOS dimension when scaled to nanometer dimension, many physical barriers arise. In sub-100 nm scale, MOSFET has new variants as SOI implementation and double gate.

 

Keywords: Silicon on insulator (SOI), short channel effect (SCE) [2], buried oxide (BOX)

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Published

2019-08-09

Issue

Vol. 2 No. 1-2-3 (2012)

Section

Articles

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