Design, Implementation and Comparative Analysis of Different 8-Bit Multipliers Based on Power, Delay and Hardware Utilization

Abstract

Multipliers play important role in the digital VLSI design. Computational Speed, power consumption, and area are the major parameters on which the performance of the device depends. In digital design, there are different multiplication methods or algorithms. Each algorithm is having its own advantage and disadvantage. In this paper, implementation of five different types of 8-bit multipliers namely Array multiplier, Booth multiplier, Truncated multiplier, Pipelined multiplier, and Vedic multiplier has been done. All these multipliers are compared based on power, delay, and area. Designing and implementation of multipliers has been done in Verilog, which is a hardware description language, and these have been synthesized using the Xilinx ISE tool. Pipelined multiplier has minimum delay and Array multiplier takes maximum delay among all the multipliers demonstrated in this work. Though Pipelined multiplier shows best performance in delay, but it shows maximum power consumption for its operation, whereas the Vedic multiplier consumes least power. Similar trend of Pipelined multiplier and Vedic multiplier are demonstrated at the area front, which means Pipelined multiplier needs more hardware and Vedic multiplier needs very less hardware for their implementation.