A Time Domain Analysis on Chip High Speed VLSI Optical Interconnection Network

Authors

  • Abhishek Sharma Department of Electronics and Communication Engineering, Jaipur National University, Jaipur, Rajasthan, India
  • Sudhir Kumar Sharma Department of Electronics and Communication Engineering, Jaipur National University, Jaipur, Rajasthan, India

DOI:

https://doi.org/10.37591/jovdtt.v8i3.577

Abstract

Intrachip optical interconnects (OIs) have the potential to outperform electrical wires and to ultimately, solve the communication problem, and to obtain high-performance integrated circuits. In this study, the International Technology Roadmap for Semiconductors (ITRS) is used as a reference to fulfill the requirements of silicon-based ICs must satisfy to successfully perform copper electrical interconnects (IEs).

 

Keywords: Integrated optoelectronic circuits, optoelectronics, optical interconnects (ICs), silicon photonics

Cite this Article

Abhishek Sharma, Sudhir Kumar Sharma. A Time Domain Analysis on Chip High Speed VLSI Optical Interconnection Network. Journal of VLSI Design Tools & Technology. 2018; 8(3): 36–44p.

 

Downloads

Published

2018-12-26

Issue

Vol. 8 No. 3 (2018)

Section

Articles

License

Thank you for submitting the manuscript to the Journal of VLSI Design Tools & Technology. With the online journal management system that we are using, you will be able to track its progress through the editorial process by logging in to the journal web site:

An author may request for withdrawal of his/her manuscript, within a week's
time  (w.e.f. the date of submission of the manuscript). The Author is
recommended to follow strictly the Instructions in Manuscript Withdrawal
Policy (As per URL given below)
http://stmjournals.com/pdf/manuscript%20withdrawl.pdf


If you have any questions, please contact me. Thank you for considering this
journal as a venue for your work.