Design of Three-Stage Pipelined Floating Point Arithmetic Operators

Authors

  • Shaikh Shoaib Arif Research Scholar (VLSI), Department of Electronics and Telecommunication Engineering, Dr. Babasaheb Ambedkar Marathwada University, Aurangabad, Maharashtra, India
  • B. B. Godbole Department of Electronics Engineering, Karmaveer Bhaurao Patil College of Engineering, Satara, Maharashtra, India

DOI:

https://doi.org/10.37591/jovdtt.v8i2.598

Abstract

Some embedded systems perform signal processing operations (Fourier transform, filtering) as for example for the recognition voice, high quality audio and control of critical systems (airplane, rocket). This type of operation may require the use of floating numbers. This paper presents the hardware implementation of floating point arithmetic operators for addition, subtraction, multiplication using the IEEE-754 single precision format. Proposed architecture follows two different RTL approach, Melay FSM  and multiplexer based approach. The RTL is developed in Verilog and design is implemented in Xilinx Virtex 7 series. The area and speed compared where mux based design claims lesser area then FSM based approach at the cost of marginal speed.

Keywords: IEEE-754, Melay FSM, RTL, Verilog, Xilinx

Cite this Article
Shaikh Shoaib Arif, B.B. Godbole. Design of Three-Stage Pipelined Floating Point Arithmetic Operators. Journal of VLSI Design Tools & Technology. 2018; 8(2): 9–22p.


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Published

2018-05-09

Issue

Vol. 8 No. 2 (2018)

Section

Articles

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