Comparative Analysis of Different SRAM Cells Architecture at 70 nm

Authors

  • Nidhi Tiwari Department of Electronics and Communication Engineering, Vivekananda Global University, Jaipur, Rajasthan, India
  • Vaibhav Neema Department of Electronics and Communication Engineering, Institute of Engineering and Technology, Devi Ahilya University, Indore, Madhya Pradesh, India
  • Kamal J. Rangra Transducers and Actuators Group, CSIR-Central Electronics Engineering Research Institute, Pilani, Rajasthan, India
  • Yogesh Chandra Sharma Department of Physics, Vivekananda Global University, Jaipur, Rajasthan, India

DOI:

https://doi.org/10.37591/jovdtt.v8i2.686

Abstract

There are severe constraints which affect the real time operation of SRAM cells. With increasing demand of device scaling, the performance parameters of SRAM cells are affected. Our main purpose is to maintain performance of memory cells in real time operation. Here, we considered three basic parameters stability, leakage current and delay for compression of various SRAM cell architectures. In this paper, we considered conventional 6T, asymmetric 7T, asymmetric 8T and asymmetric 9T SRAM cells and calculated various design parameters using simulation of mentioned circuits at 70 nm. Here, to find better parametric compression, different cell ratios were also considered. From the simulation results, it is found that using MTCMOS design techniques, leakage current is effectively suppressed but on account of delay penalty. The delay penalty can also be minimized by selecting properly sized inverter cell.


Keywords: SRAM, stability, SNM, MTCMOS

Cite this Article
Nidhi Tiwari, Vaibhav Neema, Rangra
Kamal J et al. Comparative Analysis of
Different SRAM Cells Architecture at
70 nm. Journal of VLSI Design Tools &
Technology. 2018; 8(2): 33–41p.



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Published

2018-07-20

Issue

Vol. 8 No. 2 (2018)

Section

Articles

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