Vol. 3 No. 2 (2013)

Articles

• Cogeneration of Fast Motion Estimation Processor and Algorithms Using Loss Less Compression

  M. Viji, S. Chitra

  1-5

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• Comparative Study of a 32 bit Clock Gated ALU based on Carry Skip Adder and Ripple Carry Adder

  Ankit Mitra

  6-11

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• Design of Low Power Folded Cascode Current Mirror CMOS OTA and Implementation of 2nd Order Gm-C IF Filter with Analysis of S-Parameter

  Kehul A. Shah, N.M. Devashrayee

  12-23

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• Logic Optimization Algorithm based on Shannon’s Expansion: Reduction in Area, Power and Delay for Pass Gate Implementation

  Usha Sandeep Mehta, Vaishali Dhare, Harikrishna Parmar, Rahul A. Shah

  24-34

  • Requires Subscription PDF (USD 30)