Efficient ADP Scheme for DWT Computation

Abstract

Abstract

In this paper, the lifting and flipping scheme for discrete wavelet transform (DWT) computation and proposed an area delay efficient lifting based DWT architecture. In this computation huge number of multipliers and adders are saved when lifting based 2-D DWT architecture implemented. The derived full-parallel lifting-based 1-level 2-D DWT structure involves half number of less multiplier than the flipping-based 2-D DWT structure. Compared with the existing lifting-based structure, the proposed lifting-based structure involves 21.38% less area-delay-product (ADP) for block size 32.

Keywords: VLSI, Discrete hardware, DWT, Lifting scheme

Cite this Article

Vikas Tiwari. Efficient ADP Scheme for DWT Computation. Journal of Microelectronics and Solid State Devices. 2018; 5(3): 22–26p.