Design and Analysis of Energy-Efficient GDI Cell and Its Impact on Multipliers

Abstract

VLSI design technology suffers from three major issues such as area, speed and power. Among these issues, power is a serious concern that is yet to be considered. So, in this paper, power is concerned more as compared to area and speed. GDI (gate diffusion input) is one of the common techniques used in VLSI design systems to reduce power consumption. Due to its high performance and less area overhead, this technique is extensively used in many low-power applications. This paper presents three different multipliers such as array multiplier, Wallace tree multiplier and Dadda multiplier based on GDI technique. The proposed designs were done using DSCH2 and were simulated using 120 nm technology in Microwind EDA tool with a supply of 1.5 V.

Keywords: GDI, VLSI, CMOS, array multiplier, tree multiplier, power consumption