| Issue | Title | |
| Vol 5, No 2 (2015) | 4-Bit Magnitude Comparator Design using Different Logic Styles | Abstract |
| Vipul Mittal, Tanushree ., Madhulika Arora, Meenakshi Yadav, Sakshi Chaudhary | ||
| Vol 8, No 2 (2018) | A Common Mode Scan Based BIST for Stuck-at-Fault and Path Delay Fault | Abstract |
| Ram Vishnu S, Yasodha T | ||
| Vol 4, No 2 (2014) | A Cuckoo Search based Approach for Solving Standard Cell Placement Problem | Abstract |
| amanpreet singh, maninder kaur | ||
| Vol 6, No 1 (2016) | A Differentiator Based on Second Generation Current Controlled Conveyor | Abstract |
| A. Kumar, R. Pandey | ||
| Vol 8, No 3 (2018) | A Dual Material Control Gate Tunnel Field Effect Transistor for an Asymmetric Doping at Source and Drain Regions | Abstract |
| Pratiksha Kharat | ||
| Vol 3, No 1 (2013) | A High Performance Reference Circuit with Optimized Input Offset Operational Amplifier using Device Mismatch Model | Abstract |
| Anil K. Saini, Kapil K. Rajput, Sanjay Singh, Ravi Saini | ||
| Vol 4, No 3 (2014) | A Low Power Variable Gain Amplifier for Biomedical Application | Abstract |
| dipesh panchal, amisha naik, N M Devshrayee | ||
| Vol 4, No 1 (2014) | A New Current Mode Quadrature Oscillator using Current Differencing Transconductance Amplifier (CDTA) | Abstract |
| Sajal K. Paul | ||
| Vol 3, No 1 (2013) | A New High Speed Low Power 1 Bit Full Adder | Abstract |
| Angshuman Chakraborty, Sambhu Nath Pradhan | ||
| Vol 3, No 1 (2013) | A New Sub-1 Volt Reference for Low Voltage Application Based on MOSFET’s Threshold Voltage Extractor | Abstract |
| Anil K. Saini, Megha Agarwal | ||
| Vol 6, No 2 (2016) | A New TGC-Differential Input Stage to Modify Dynamic Comparator | Abstract |
| anurag sharma, gurinderpal singh | ||
| Vol 11, No 2 (2021) | A Nobel Approach of Designing A 4 Bit Carry Skip Adder Using Reversible Logic | Abstract |
| Pinaki Satpathy, Santanu Maity | ||
| Vol 3, No 3 (2013) | A Novel 4:1 Multiplexer Design using Power Minimization Technique based Domino Logic | Abstract |
| Vignesh M, Naveen R | ||
| Vol 7, No 1 (2017) | A Novel Approach Based On-Chip High Speed Optical Interconnection Network | Abstract |
| abhishek sharma, sudhir kumar sharma, pramod sharma | ||
| Vol 7, No 1 (2017) | A Novel Approach for 3D Floor Planning in VLSI with Minimum Dead Space using a New Topological Structure | Abstract |
| ajoy kumar khan | ||
| Vol 9, No 3 (2019) | A Novel Conflict-Free Efficient Memory-Based Real FFT Processor using UTB | Abstract |
| Rajasekhar Turaka | ||
| Vol 4, No 2 (2014) | A Novel Current-Mode Quaternary Multiplier with Indian Vedic Architecture | Abstract |
| ashish s shende, deepak r dandekar | ||
| Vol 4, No 1 (2014) | A Novel Design for Power Reduction in Arithmetic Circuits using MTCMOS Technology | Abstract |
| Vijayanand K, Sureshkumar N | ||
| Vol 5, No 2 (2015) | A Novel Efficient VLSI Architecture for Matrix Multiplication using Compressor-based Multiplier | Abstract |
| Kirti Sharma, Anushree . | ||
| Vol 6, No 1 (2016) | A Novel Logic Styles used for Leakage Power Reduction in MOS Integrated Circuit | Abstract |
| M. Hulkey, H. Upadhyay, K. Sujhatha | ||
| Vol 13, No 1 (2023) | A Reliable Low Standby Power 6T SRAM Cell | Abstract |
| K Joseph Thanusha, Anusha Achhina, Dedeepya Padakanti | ||
| Vol 6, No 1 (2016) | A Review for Power Optimization in MOS Devices using Different Logic Styles | Abstract |
| M. Hulkey, H. Upadhyay, K. Sujatha | ||
| Vol 5, No 3 (2015) | A Review on Charge Pump Circuits for PLL Applications | Abstract |
| D. Shekhar, A. Raman | ||
| Vol 8, No 2 (2018) | A Review on FPGA Parallel Architecture for Object Detection | Abstract |
| Sudhir Dagar, Geeta Nijhawan | ||
| Vol 10, No 3 (2020) | A Review on Mechanization of Process Planning for Automated Fiber Placement | Abstract |
| Akanksha Gupta | ||
| 1 - 25 of 237 Items | 1 2 3 4 5 6 7 8 9 10 > >> | |
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