Performance Analysis of 3T DRAM Using FinFET Based with Leakage Reduction Techniques at 45 nm Technology

Abstract

The proposed area of research is to reduce the power consumption, leakage voltage, leakage current and leakage power of DRAM while maintaining the competitive performance. The Fin FET approach is used in DRAM for high performance. Fin type field effect transistors (Fin FET) are capable substitutes for bulk CMOS at the nano-scale. Fin FET are double gate device. A Fin FET uses an intrinsic body. It greatly suppresses the device-performance variability caused by the fluctuation in the number of dopant ions, while a planar-bulk MOSFET requires a heavily doped channel which causes serious process variability. A Fin FET based DRAM memory design has been proposed as an alternative solution to the bulk devices. Fin FET is suitable for future nano-scale memory circuit design due to its reduced short channel effects (SCE) and leakage current. Fin FET DRAM cells can reduce area and leakage power. Z` `By using the Fin FET CMOS technology we investigate that it provide low leakage and high performance operation by utilizing high speed, low Vt transistor for logic cell and low leakage.

Keywords: DRAM, Fin FET, CMOS, Leakage power, Leakage current

Cite this Article

Bharat Tripathi, Saurabh Khandelwal. Performance Analysis of 3T DRAM Using FinFET Based with Leakage Reduction Techniques at 45 nm Technology. Journal of VLSI Design Tools & Technology. 2017; 7(3): 28–34p.