Analysis and Characterization of Circuits for Leakage Power Reduction at Sub-50 nm in CMOS Circuits

Abstract

This paper analyzes various techniques to decrease leakage power in complementary metal oxide semiconductor (CMOS) very large scale integration (VLSI) circuits, because due to continuous scaling of CMOS technology there is improvement in speed of semiconductor devices and the side effect of this scaling is leakage power. With the development of technology in CMOS VLSI Circuit, length of transistors has been reduced and speed of operation is increasing simultaneously. As the technology is increasing, transistor length is reducing in the CMOS VLSI circuit. The leakage power has been taken as a major problem as the scaling has been extended into ultra-deep sub-micron technology (UDSM). The reduction in the length of the transistor decreases the threshold voltage, and this causes the sub-threshold current increases. Designing of nanoscale CMOS VLSI circuit and the leakage power reduction are very challenging task. this leakage current should be shrunk for the trouble free operation of the desired circuits. Beforehand for leakage power reduction many methods have been used like leakage feedback technique, sleepy keeper technique, sleep transistor technique, MTCMOS (multi-threshold CMOS), dual sleep approach. As we approach UDSM design then the total chip power consumption depends on the leakage power of the circuit. This paper analysis differentiates the past work for leakage power reduction with proposed work and this paper gives better result which is quite different from the past technology because of the parameters like threshold voltage (Vth), channel width and length. The proposed work has been completed on the sub-50 nm technology file with the tool used is LTspice XVII