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Impact of Spacer Engineering on SOI Junctionless FET Performance Using TCAD Simulation

P. Sasikala, Priscilla Scarlet, K. K. Nagarajan, R. Srinivasan


In this paper, the impact of spacer engineering on 10 nm gate length planar SOI (Silicon On Insulator) junctionless transistor performance is studied using Sentaurus TCAD simulator. Spacer length and spacer permittivity of the device are taken as two controllable parameters. DC performance metrics, ION, IOFF, ION/IOFF ratio, unity gain frequency (fT) and non quasi static delay (NQS) are investigated for various spacer lengths and spacer permittivity. The simulation results suggest that with high-k spacer and with minimum spacer length better ION/IOFF ratio can be achieved. fT (unity gain frequency) decreases at higher spacer lengths and at higher permittivity values. Phase delay increase with increase in frequency.


Planar, TCAD, fT, SOI junctionless FET, high-k, buried oxide (BOX)

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