Reducing Cell Density Congestion Issue in Chip Design

Abstract

Abstract

The congestion issues reduce with the help of shrinking process technologies. Here, typical placement objectives involve reducing cell density congestion in a chip design. Congestion reducing is the least understand; however, it models route ability most accurately. The congestion issue is cell density (commonly believed to be very effective) does not always work well, so here by applying the partial block technique for the cell density is among the best congestion alleviation approaches. Congestion at the global placement correlates well with the cell density congestion of detailed placement. With the help of partial block technique, optimize the area, power, and also increasing the chip level performance.

Keywords: Placement, congestion, partial blockage, cell density, alleviation

Cite this Article

S. Mohan Das, Shaik Mahammad Rafi. Reducing Cell Density Congestion Issue in Chip Design. Journal of Microelectronics and Solid-State Devices. 2019; 6(3): 11–17p.