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Design of Slew Aware Clock Distribution Network for Ultra Low Power Sub-threshold Applications

Rupali Ashok Walunj, Sachin Dattatraya Pable, Gajanan Kashiram Kharate


Clock distribution network consumes significant amount of power due to its high switching activity. The high power consumption issue can be satisfactorily addressed by the sub-threshold operation of device, however at the cost of degraded performance and magnified variability. This paper investigates the suitability of conventional clock distribution network for sub-threshold regime and proposes a novel strategy of having an optimized uniform H-tree with a pair of buffer only at sink nodes in CDN. The performance of various configurations in which the pair of buffer can be connected is investigated. Finally, the optimized uniform H-tree with CMOS buffer connected to sink node and followed by dynamic threshold MOS (DTMOS) buffer is proposed. The simulation results indicate that a tenfold time’s improvement in slew is exhibited by proposed clock distribution network with added advantage of reduced power consumption as compared to conventional clock distribution network. Along with improvement in slew, its control is utmost important to ensure reliable operation of synchronous system. Therefore variability analysis is also accentuated in this paper. The results exhibit that the proposed clock distribution network is robust compared to conventional clock distribution network. 

Keywords: Sub-threshold, Ultra Low Power (ULP), Clock Distribution Network (CDN), Dynamic Threshold MOS (DTMOS), slew

Cite this Article

R.A. Walunj, S.D. Pable, G.K. Kharate. Design of Slew Aware Clock Distribution Network for Ultra Low Power Sub-threshold Applications. Journal of VLSI Design Tools & Technology. 2019; 9(1): 22–37p.


Sub threshold; Ultra Low Power (ULP); Clock Distribution Network (CDN);Dynamic Threshold MOS (DTMOS); Slew

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Paul B. C., Agarwal A., Roy K., (2006), “Low-Power Design Techniques for Scaled Technologies,” Elsevier, Integration, the VLSI journal, 39, 64–89.

Rabey J, Chandrakasan A. and Nikoloic B., (2003), “Digital Integrated Circuits- A Design Perspective,” 2nd Edition, Prentice Hall, New Jersey, USA.

Tolbert J. R., Zhao X,. Lim S. K., Mukhopadhyay S., (2009), “Slew-Aware Clock Tree Design for Reliable Sub-threshold Circuits,” ISLPED.

Friedman E.G, (2001), “Clock Distribution Networks in Synchronous Digital Integrated Circuits,” Proceedings of IEEE, 89(5),665–692.

Choudhary S. and Qureshi S., (2010), “ Design, Modelling and simulation of H tree Clock,” Institution of Engineers Australia, Australian Journal of Electrical & Electronics Engineering, Vol 7 No 3

Chaturvedi R. and.Hu J., (2004), “Buffered Clock Tree for High Quality IC Design,” International Symposium on Quality Electronic Design, IEEE.

Reuben J., Zackriya M., Harish V., Kittur M., Shoaib M., (2015), “A Buffer Placement Algorithm to Overcome Short-Circuit Power Dissipation in Mesh Based Clock Distribution Network,” Engineering Science and Technology, an International Journal, Vol.18, No.2, 135-140.

Islam R., Guthaus M., (2015) “Low Power Clock Distribution Using A Current Pulsed Clocked Flip-Flop,” IEEE Transactions on Circuits and Systems- I Regular Papers, Vol.62, No. 4.

Gaioni L., Canio F, Manghisoni M., Ratti L., V.. Traversi G, (2015), “Design and Test of Clock Distribution Circuits for the Macro Pixel ASIC,” Nuclear Instruments and Methods in Physics Research, Elsevier Science.

Tenace V., Miryala S., Calimera A., Macii A., Macii E.,. Poncino M, (2014) , “Row-Based Body Bias Assignment for Dynamic Thermal Clock-Skew Compensation,” Microelectronics Journal, Vol. 45, No.5, 530-538.

Dave M., Jain M., Baghini M., Sharma D.,2013 “A Variant Tolerant Current Mode Signalling Scheme for On Chip Interconnects,” IEEE Transactions on Very Large Scale (VLSI) Systems, Vol. 21, No.2.

Abdelhadi A., Ginosar R., Kolodny A and Friedman E., (2013), “Timing Driven Variation Aware Synthesis of Hybrid Mesh / Tree Clock Distribution Networks,” Integration, the VLSI journal, Vol.46, No.4,382–391.

Rajaram A., Jiang H. and Mahapatra R.,2006, “Reducing Clock Skew Variability via Cross links,” IEEE Transactions on Computer-Aided of Integrated Circuits and Systems, Vol. 25 ,No. 6.

Tellez G.E and Sarrafzadeh M., (1997), “Minimal Buffer Insertion in Clock Trees with Skew and Slew Rate Constraints,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16, No. 4.

Kil J., Gu J., and Kim C. H., (2006), “A High – Speed Variation – Tolerant Interconnect Technique for Sub-threshold Circuits using Capacitive Boosting,” International Symposium on Low Power Electronics and Design, (ISLPED'06), doi: 10.1145/1165573.1165590

Zhao X, Tolbert J, Liu C., Mukhopadhyay S., and Kyu Lim S, (2011) , “Variation-aware Clock Network Design Methodology for Ultra-Low Voltage (ULV) Circuits,” IEEE Transaction on Computer Aided Design of Integrated Circuits and System.

Seok M, Blaauw D., Sylvester D., 2010, “Clock Network Design for Ultra-Low Power Applications,”ISLPED’10, Austin, Texas, USA, 18–20.

Pable S. and Hasan M, (2012), “Ultra-Low-Power Signaling Challenges for Sub-threshold Global Interconnects,” Integration, the VLSI Journal, Elsevier, Vol.45, No.2,186-196.

Sitik C., Lerner S. and Taskin B., (2014) “Timing Characterization of Clock Buffers,” IEEE International Conference on Computer Design (ICCD).

Zhai B., Pant S., Nazhandali L.,Hanson S, Olson J, Reeves A, Minuth

M.,Helfand R, Austin T.,Sylvester D., Blaauw D., (2009), “Energy-efficient subthreshold processor design,” IEEE Transactions on VLSI systems, Vol. 17, No. 8, pp. 1127–1137.

Kim C. H, Soeleman H. and Roy K., (2003) , “Ultra-Low Power DLMS Adaptive Filter for Hearing Aid Applications,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 11, No. 6, pp1058-1067.

Wang, A., Calhoun, B. H., and Chandrakasan, A. P., (2006),‘Sub- Threshold Design for Ultra Low-Power Systems, 1st ed. New York: Springer

Wei-Khee L.,.Kok-Siang T and Ying-Khai T., (2009), “A Study and Design of CMOS H-Tree Clock Distribution Network in System-on-Chip,” 8th International Conference on ASIC, IEEE, doi: 10.1109/ASICON.2009.5351254

Berkeley Predictive Technology Model, UC Berkeley Device Group. [Online]. Available: /http//

International Technology Roadmap for Semiconductors, 2005.

Li X.C., Mao, J.F, Huang H.F., Liu Y, (2005), “Global interconnect width and spacing optimization for latency , bandwidth and power optimization”, IEEE Transaction on Electron Devices, Vol. 52, No. 10,2272-2279.

Jamal O. and Naeemi A., “Evolutionary and Revolutionary Interconnect Technologies for Performance Enhancement of Sub-threshold Circuits,” International Interconnect Technology Conference (IITC), IEEE, doi: 10.1109/IITC.2010.5510733

Soeleman H., Roy K., Paul B., (2001), “Robust Subthreshold Logic for Ultra-Low Power Operation” IEEE transactions on very Large Scale Integration (VLSI) Systems, Vol. 9, No. 1.



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