A Review on Charge Pump Circuits for PLL Applications

Authors

  • D. Shekhar Department of ECE, Dr. B.R. Ambedkar National Institute of Technology, Jalandhar, Punjab, India
  • A. Raman Department of ECE, Dr. B.R. Ambedkar National Institute of Technology, Jalandhar, Punjab, India

DOI:

https://doi.org/10.37591/jovdtt.v5i3.1645

Abstract

This paper presents a review on various architectures of charge pumps (CP) for high speed Phase-locked loop (PLL) applications. The different nonlinear marvels that influence the execution of PLL in view of the CPs circuit are examined. The various high performance CP circuits with reference voltage source, reference current source are analyzed that reduces the problems associated with the traditional charge pump circuit that consists leakage current, clock feed-through, charge sharing, charge injection, charge/discharge current mismatch, output ripple, phase error due to current mismatch, and spurious jump phenomenon. 

Keywords: Phase locked loop (PLL), charge pump (CP), charge injection, clock feed through, current matching

Cite this Article

D. Shekhar, A. Raman. A Review on Charge Pump Circuits for PLL Applications. Journal of VLSI Design Tools and Technology. 2015; 5(3): 1–11p.


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Published

2019-03-11

Issue

Vol. 5 No. 3 (2015)

Section

Articles

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