A Novel 4:1 Multiplexer Design using Power Minimization Technique based Domino Logic

Abstract

Domino circuits are widely used these days in the design of modern-day microprocessors because of their high speed and less area overhead compared to static logic style. In this paper, a new domino-based 4:1 multiplexer circuit has been designed which finds extensive use in register files and execution units where large amounts of data have to be broken into smaller chunks so that the processor can manipulate it more easily and gives back the processed data in pieces when it finishes processing it. Simulations have been performed using the Microwind EDA tool in 0.12 µm CMOS technology at a supply voltage of 1.5 V. The proposed design shows 24.52 and 20% reduction in power and delay when compared with basic domino circuit topology and 10.41 and 38.45% reduction in power and delay when compared with adaptive pseudo dual keeper (APDK) design with a slight area overhead.

 Keywords: Domino, multiplexer, APDK, static logic, dynamic logic