High-speed CMOS ADCs Design
DOI:
https://doi.org/10.37591/jovdtt.v2i1-2-3.2952Abstract
This paper presents the design of high-speed subranging and flash analog to digital data converters (ADC) including the design of efficient operational amplifier to meet the performance requirements of these data converters for the specifications laid down targeted to the SCL 1.2 μm CMOS Foundry. The design starts from the specification of the circuit, its theoretical analysis for the parameter estimations of the transistors as well as the circuit’s design. Its simulation studies with design iterations were carried out using EDA tools. Pre- and post-layout electrical behavior verification of the circuit was carried out for the circuits from its layout as well as netlist extracted circuit from its schematic. Best performance has been achieved by the design iterations as presented in the paper.
Keywords: Flash and subranging ADC, operational amplifier, comparator and subtractor
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