Implementation of 32 bit parallel adder using XILINX IPCORES A Case Study

Authors

  • Khaleel U Rehman Associate Professor, Dept of  Electronics & Communication Engineering,Nalla Malla Reddy Engineering College,Hyderabad. http://orcid.org/0000-0001-6558-3380
  • Salauddin Mohammad Associate Professor Department of ECE, J.B.Institute of Engineering & Technology, Hyderabad, Andhra Pradesh, India
  • Mudassar Basha Assistant Professor Department of ECE, B.V.R.I.T, Hyderabad, Andhra Pradesh, India

DOI:

https://doi.org/10.37591/jovdtt.v10i2.4039

Keywords:

IP, FPGA, VHDL, Xilinx.

Abstract

The paper aims to target the Xilinx intellectual property (IP) cores and the methodology that allows in the easy way of implementing the IP cores and its functionalities and the interface with the recent Xilinx FPGA’s. The proposed work compares the results obtained with the conventional Xilinx programming and the IP cores which are associated with it. VHDL programming style is used to describe the hardware and its functionality.

 

Keywords: Adder, IP, FPGA, VHDL, Xilinx

Author Biography

  • Khaleel U Rehman, Associate Professor, Dept of  Electronics & Communication Engineering,Nalla Malla Reddy Engineering College,Hyderabad.

    Dr.B.Khaleelu Rehman working as Associate professor in Nalla Malla Reddy Engineering College, Hyderabad. Received Ph.D. degree from University of Petroleum & Energy Studies, Dehradun and M.Tech from Shadan College of Engineering & Technology, affiliated to JNTU Hyderabad in VLSI System Design. He is having 12 years of teaching experience out of which 8 years in the University of petroleum & Energy studies, Dehradun. He has published 1 SCI journals, 11 Scopus journals, 2 International book chapters and 1 Indian patent. He is reviewer and editorial member for several reputed journals and also active member in several professional societies He has conducted 6 workshops in the UPES and attended 12 workshops/short term courses/FDPs.He has Awarded certificate of Appreciation from R & D department, UPES during Academic year 2017-2018 and 2016-2017.He was the session chair for International Conference on Intelligent Communication, Control and Devices Dehradun, India, (Springer Conference).ICICCD-2016,ICICCD-2017 and ICICCD-2018. His area of interest includes Digital Signal processing, VLSI Design, Digital VLSI Architectures and Analog Circuits.

References

Kumar, Adesh, Gaurav Verma, Mukul Kumar Gupta, Mohammad Salauddin, B. Khaleelu Rehman, and Deepak Kumar. "3D Multilayer Mesh NoC Communication and FPGA Synthesis." Wireless Personal Communications 106, no. 4 (2019): 1855-1873.

Reddy, K. Venkata Siva, P. Vishnu Kumar, K. Maheswari, and B. Khaleelu Rehman. "Design and Verification of 16-Bit Vedic Multiplier Using 3: 2 Compressors and 4-Bit Novel Adder." In Proceeding of International Conference on Intelligent Communication, Control and Devices, pp. 723-732. Springer, Singapore, 2017.

Rehman, B. Khaleelu, Adesh Kumar, and Paawan Sharma. "Modeling and Simulation of ECG Signal for Heartbeat Application." Intelligent Communication, Control and Devices. Springer, Singapore, 2018. 503-511.

Garrido, Mario, and Jesus Grajal. "Efficient memoryless CORDIC for FFT computation." 2007 IEEE International Conference on Acoustics, Speech and Signal Processing-ICASSP'07. Vol. 2. IEEE, 2007.

Rehman, B. K., Kumar, A., Mohammad, S., Basha, M., & Reddy, K. V. S. (2020). Detection of DTMF by Using Goertzel Algorithm and Optimized Resource-Sharing Approach. In Intelligent Communication, Control and Devices (pp. 851-856). Springer, Singapore.

Mohammad, Salauddin, R. Seetha, S. Jayamangala, B. Khaleelu Rehman, and D. Kumar. "Implementation of FM-Based Communication System with 3-Level Parallel Multiplier Structure for Fast Transmission Using FPGA." In Intelligent Communication, Control and Devices, pp. 619-626. Springer, Singapore, 2020.

Basha, Mudasar, M. Siva Kumar, Vemulapalli Sai Pranav, and B. Khaleelu Rehman. "Approach to Find Shortest Path Using Ant Colony Algorithm." In Intelligent Communication, Control and Devices, pp. 1243-1252. Springer, Singapore, 2018.

Lysaght, Patrick, et al. "Enhanced architectures, design methodologies and CAD tools for dynamic reconfiguration of Xilinx FPGAs." 2006 International Conference on Field Programmable Logic and Applications. IEEE, 2006.

Paulsson, Katarina, et al. "Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems." ReCoSoC. 2007.

Crockett, Louise H., et al. The Zynq Book: Embedded Processing with the Arm Cortex-A9 on the Xilinx Zynq-7000 All Programmable Soc. Strathclyde Academic Media, 2014.

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Published

2020-09-15

Issue

Vol. 10 No. 2 (2020)

Section

Articles

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