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Vol. 7 No. 1 (2017)
Vol. 7 No. 1 (2017)
Published:
2019-08-09
Articles
Implementation of Carry Select Adder with Reduced Area Scheme
pinaki satpathy
1-5
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A Novel Approach for 3D Floor Planning in VLSI with Minimum Dead Space using a New Topological Structure
ajoy kumar khan
6-17
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(USD 30)
Comparative Analysis of Phase Frequency Detector for Phase-Locked Loops
Gunjankumar R Modi, Priyesh P Gandhi, Nilesh D Patel
18-28
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Low-Power Design of Content Addressable Memory using Master Slave Match Line Architecture
boda venkata lakshmi, Boggavarapu satish kumar
29-34
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Analysis and Implementation of Folding and Interpolating Analog to Digital Converter using Submicron CMOS Technology
rahulkumar S suthar, priyesh P gandhi
35-40
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A Novel Approach Based On-Chip High Speed Optical Interconnection Network
abhishek sharma, sudhir kumar sharma, pramod sharma
41-48
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Enhancement in RMPA Parameters using Slotted Rhombus Connected Square Shaped Antenna with Left Handed Metamaterial
ram kishor sharma, mahendra kumar pandey, sandeep kumar agrawal
49-54
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