Analysis and Implementation of Folding and Interpolating Analog to Digital Converter using Submicron CMOS Technology

Authors

  • rahulkumar S suthar Department of Electronics and Communication, L.C. Institute of Technology, Bhandu, Mehsana, Gujarat, India
  • priyesh P gandhi

DOI:

https://doi.org/10.37591/jovdtt.v7i1.3015

Abstract

This paper presents folding and interpolating ADC with resolution of 5 bit. The simulation result is carried out using 0.18 μm CMOS process technology with supply voltage 1.8 V. This folding and interpolating ADC consumes less power than other, and it is 10 mW. The rate of conversion is 50 MS/S. So, it is suitable for low power application and medium resolution portable devices.

 

Keywords: Folding ADC, interpolating, ADC, low power comparator

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Published

2019-08-09

Issue

Vol. 7 No. 1 (2017)

Section

Articles

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