kumar, sampath, JSS Academy of Technical Education, Noida-201301, India
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Vol 2, No 1-2-3 (2012) - Articles
Delay Minimization of 3 Cascaded Inverters with the Help of Logical Effort and Transistor Sizing
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eISSN: 2249–474X
Journal of VLSI Design Tools & Technology (JoVDTT)
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