Challenges Beyond 100 nm MOS Devices

Authors

  • savita maurya Department of Electronics and Communication Engineering, Integral University, Lucknow, India
  • sarita Shrivastava

DOI:

https://doi.org/10.37591/jovdtt.v6i2.2981

Abstract

MOS devices have been aggressively scaled down in research and in the production in last few years. Sub-100 nm feature size MOS circuits have been used for many. However, many serious limitations and problems emerged with such a small geometry MOSFETs are used to realize very large-scale integrated circuits. Commercial 45 nm technology node, has much higher production cost and it is one of the greatest concern for scaling down devices beyond 10 nm. This paper deals with challenges and limits of beyond 100 nm technology. Possible limiting factors for the scaling of devices have also been elaborated.

 

Keywords: MOS technology, device scaling, semiconductor manufacturing

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Published

2019-08-09

Issue

Vol. 6 No. 2 (2016)

Section

Articles

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