Design and RTL Implementation for AHB-APB Bridge on SoC

Abstract

The focus of this research is to design and implement an interconnection protocol with 32-bit read/write data which operates on AMBA AHB-APB bridge. With the advent of scaling technology, embedded system focuses more on low-power dissipation and SoCs. Hence processors and routing protocols which focus on low-power design by ARM have gained popularity. In high-speed communication modules, the protocol works efficiently but has limitations with device operating at low speed. AHB-APB bridge standard can be used to alleviate this issue. While performing any read/write operation AHB must wait for the acknowledgement signal from APB. APB transactions are converted in to AHB. In addition of these features, an error bit generates in case of any data mismatching during the data transfer between AHB to APB. Error bit becomes 1 if there is any mismatch in data, else it becomes 0. AMBA AHB-APB is designed with the help of Verilog and its synthesis results in a total hierarchy power consumption of 0.041 mW, and leakage power 0.036 mW and minimum data path delay is 5.690 ns, timing and functional simulation modeling is done using Xilinx simulator 14.7, Chip scope pro.

Keywords: Verilog, AHB, APB, FSM, Chip Scope pro