Design of Booth Encoded Multi-Modulus {2n-1, 2n, 2n+1} RNS Multiplier

Abstract

Multiplication, a very important arithmetic operation, is finding a great use these days in various applications (especially DSP, multimedia and image processing). Due to advances in technology and increasing needs for high-speed calculations, it has become really necessary and important to design a fast efficient multiplier. A productive method to speed up the multiplication is reduction in the Partial Product (PP) array. In this paper, the design of 8, 16 and 32 bit RNS multiplier based on Radix-4 Booth encoding is presented. The results of simple Booth multiplier are compared to a Booth encoded Residue Number System (RNS) multiplier. A significant improvement in terms of speed and area utilization is observed when Booth is applied to RNS. Pipelining has been incorporated in the architectures to boost the speed further. The designs are described in Verilog HDL, simulated and synthesized on Xilinx 14.5, targeted on Spartan 3E FPGA device.

Keywords: Booth algorithm, Radix-2, Radix-4, Radix-8, multiplication, Residue Number System, pipelining