Implementation of Carry Select Adder with Reduced Area Scheme

Authors

  • pinaki satpathy Department of Electronics and Communication Engineering, Haldia Institute of Technology, I.C.A.R.E. Complex, HIT Campus, Haldia, West Bengal, India

DOI:

https://doi.org/10.37591/jovdtt.v7i1.3011

Abstract

Addition is the heart of arithmetic unit and the arithmetic unit is often the work horse of a computational circuit. So, adders play a key role in designing an arithmetic unit and also many digital integrated circuits. Carry select adder (CSLA) is one of the fastest adders used in many data processors and in digital circuits to perform arithmetic operations. But CSLA is area-consuming because it consists of dual ripple carry adder (RCA) in the structure. To reduce the area of CSLA, a CSLA with binary to excess-1 converter is already designed which reduces the area of adder. But there are other techniques to design a CSLA to reduce its area. One of such technique is using an add-one circuit technique. This paper proposes the design of square root CSLA (SQRT CSLA) using add one circuit with significant reduction in area.

 

Keywords: CSLA, combinational circuit, adders, BEC, D-latch

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Published

2019-08-09

Issue

Vol. 7 No. 1 (2017)

Section

Articles

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