A Novel Approach for 3D Floor Planning in VLSI with Minimum Dead Space using a New Topological Structure

Abstract

Floor planning is a key issue in VLSI physical plan. The floor planning issue can be defined as that a given arrangement of 3D rectangular pieces while limiting reasonable cost capacities. Here, we are focusing on the minimization of the aggregate volume of 3D bite the dust. In this paper, another initial topological structure is presented utilizing weighted coordinated chart of a floor planning issue in 3D VLSI physical plan. In any case, here the principle question is whether this structure is compelling (or not). For this, the possibility of another calculation is proposed to limit the volume of 3D bite the dust in floor planning issue utilizing this new representation procedure. It is intriguing to see that our proposed structure is likewise proficient to ascertain the aggregate volume and position of the dead spaces if they exist. The trial consequences of the new calculation are appeared in the following.

Keywords: Floor planning, 3D rectangular block, weighted directed graph, topological structure, dead space