Design and Simulation of 4-bit Multiplier using Carry Look-Ahead Adder at Transistor Level

Authors

  • Charan Ukku Student, Department of Electronics and Communication Department Audisankara College of Engineering and Technology Gudur
  • Dhanunjaya Karumanchi Head of the Department, Department of Electronics and Communication, Audisankara College of Engineering and Technology, Gudur
  • Venkatachalam K. Assistant Professor, Department of Electronics and Communication, Audisankara College of Engineering and Technology, Gudur

Keywords:

Multiplication, Schematic, Transistor, Simulation, Hierarchical

Abstract

Multiplication is a basic operation performed in the Arithmetic Logic Unit, Digital signal processing, Floating-point unit and Application specific integrated circuits. This paper deals with the design and simulation of the 4-bit multiplier using a carry look-ahead adder at the transistor level. The total design process involves hierarchical implementation. Where the basic gate operations like AND, OR, NOT, and XOR are repeatedly used for designing the entire circuit. So, the schematic of these basic gates is first designed and then a symbol is created concerning the schematic designed. The simulation is going to be done for the 4-bit multiplication operation. And the preferred technique is designed and simulated using LT spice XVII at 22nm technology.

References

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Mehedi Hasan, Parag Biswas, Shihabul Alam, et, al. “High Speed and Ultra Low Power Design of Carry-Out Bit of 4-Bit Carry Look-Ahead Adder.”10th International Conference on Computing, Communication and Networking Technologies (ICCCNT); 2019 July 6-8; IIT – Kanpur, India. US: IEEE Publisher ; 2019.

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Published

2022-03-21

Issue

Vol. 11 No. 3 (2021)

Section

Articles

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