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Analysis and Characterization of Different Topologies of Dynamic Latch based CMOS Comparators for Delay, Offset and Power

Vijay Savani, N M Devashrayee


This paper presents the analysis and characterization of various topologies of dynamic latch based complementary metal oxide semiconductor (CMOS) comparator. Various comparator topologies like resistor divider comparator (RDC), differential pair comparator (DPC), double-tail dynamic latched comparator (DTDLC), energy efficient two-stage comparator (ETWC) and two-stage dynamic comparator (TSDL) are analyzed and compared for various performance parameters. Besides zero static power consumption, resistor divider comparator has high offset voltage and it depends on the input differential common mode voltage. Differential pair comparator having less delay and less offset voltage compared to resistor divider comparator, but requires more voltage headroom. To overcome the drawbacks of differential comparator, double-tail dynamic latch comparator can be used, but at cost of low speed and high power consumption. For low offset voltage (high resolution) applications, two-stage dynamic comparator is preferred. This paper provides analysis and characterization review about a variety of traditional dynamic latched comparator designs - in terms of delay, power, area, power delay product and input-referred offset voltage in HSPICE simulation tool using 90 nm PTM technology.


Keywords: Comparator, static comparator, dynamic comparator. double-tail comparator. two-stage dynamic comparator

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