![Open Access](https://engineeringjournals.stmjournals.in/lib/pkp/templates/images/icons/fulltext_open_medium.gif)
![Restricted Access](https://engineeringjournals.stmjournals.in/lib/pkp/templates/images/icons/fulltext_restricted_medium.gif)
Low-Complexity VLSI Hardware Design for DWPT
Abstract
Abstract
This paper presents a low-complex discrete wavelet packet transform (DWPT) architecture design for power constrained and cost sensitive healthcare applications. The multiplier-adder unit of the proposed multiplier-based designs of DWPT is replaced by the shift-add unit to reduce the area complexity of parallel structure. The proposed low-complexity multiplier-less design could be used an alternative to the existing multiplier-based design for hardware efficient realization of multi-level DWPT.
Keywords: DWPT, Hardware complexity, VLSI, multiple constant multiplication
Cite this Article
Vikas Tiwari, B.K. Mohanty. Low-Complexity VLSI Hardware Design for DWPT. Journal of Microelectronics and Solid State Devices. 2017; 4(3): 28–32p.
DOI: https://doi.org/10.37591/jomsd.v4i3.418
Refbacks
- There are currently no refbacks.
Copyright (c) 2018 Journal of Microelectronics and Solid State Devices