Survey of System-on-Chip Modular Test Approach

Abstract

The advancement in semiconductor technology over the past few decades has enabled the industry to develop new design and reuse methodologies referred as System-on-chip (SoC) design. These typically integrate heterogeneous mix of various complex analog and digital cores, with all their necessary electronic circuitry. The recent advancements have led to the use of the 3D structures (3D-SOCs) that brought along the benefits of higher performance, minimum average interconnect length, reduced power and smaller footprint. These revolutions have not only brought in new issues of design but also their testing which is becoming the major bottleneck in determining the overall system cost and a defect free delivery to market in time. To facilitate the testing of cores lying inside such complex SOCs modular approach, concurrency in test application are the only viable ways. However these come at their own costs of constraints like power, test bandwidth, resources like “through silicon vias”, BIST etc. This paper first discusses in general the various challenges in testing of core-based system chips, the associated test factors and modular test approach. It is further followed up by the various ways of addressing the challenges and the corresponding research areas.

Keywords: System on chip test, test data compression, test access architecture, embedded core based design, system on chip test architecture