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Performance Estimation of VLSI Design
Abstract
This paper explores performance estimation of VLSI design using simple RC delay model based an Elmore Delay Method. In this paper Pre-layout & Post-layout VLSI design flow for delay convergence is also shown.
Keywords
Propagation delay, NMOS, PMOS, Rise Time, Fall Time, Elmore Delay, Layout
DOI: https://doi.org/10.37591/jovdtt.v4i2.3167
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Copyright (c) 2019 Journal of VLSI Design Tools & Technology
eISSN: 2249–474X