Journal of VLSI Design Tools & Technology (JoVDTT)

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Table of Contents

Articles

Cogeneration of Fast Motion Estimation Processor and Algorithms Using Loss Less Compression M. Viji, S. Chitra

PDF 1-5

Comparative Study of a 32 bit Clock Gated ALU based on Carry Skip Adder and Ripple Carry Adder Ankit Mitra

PDF 6-11

Design of Low Power Folded Cascode Current Mirror CMOS OTA and Implementation of 2nd Order Gm-C IF Filter with Analysis of S-Parameter Kehul A. Shah, N.M. Devashrayee

PDF 12-23

Logic Optimization Algorithm based on Shannon’s Expansion: Reduction in Area, Power and Delay for Pass Gate Implementation Usha Sandeep Mehta, Vaishali Dhare, Harikrishna Parmar, Rahul A. Shah

PDF 24-34