Journal of VLSI Design Tools & Technology (JoVDTT)

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Home > Archives > Vol 1, No 1-2-3 (2011)

Table of Contents

Articles

An Explicit Approach to Compare Crosstalk Noise and Delay in VLSI RLC Interconnect Modeled with Skin Effect with Step and Ramp Input shilpi lavania, sunil kumar sharma

PDF 1-8

Analysis of Resource Utilization for a Floating-Point Complex Multiplication in FPGA anitha Mary

PDF 9-14

Analysis of VLSI Circuits Designed with Single and Dual Channel Strained Silicon MOSFETs in Nanoregime neha sharan, ashwani rana

PDF 15-20

Automatic Switch cum Fuse IC for Low Voltage, Low Power, High Performance Current Conveyors ashutosh tripathi

PDF 21-25

Gain Controlled Sinusoidal Oscillator Using Current Controlled Current Conveyors Sajal K. Paul

PDF 26-30

Modelling of Skin Effect in On-Chip VLSI RLC Global Interconnect vikas maheshwari, shilpi lavania, rajib kar, durbadal mandal, A. K. Bhattacharjee

PDF 31-44

Power Estimation for VLSI Circuits Using Neural Networks B Srinath

PDF 45-56

Time Domain Analysis in an On-chip High Speed RLCG Interconnection Network at 0.18 µm Technology Rajib Kar

PDF 57-67