Journal of VLSI Design Tools & Technology (JoVDTT)

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Home > Archives > Vol 8, No 3 (2018)

Table of Contents

Articles

Circular Retiming technique to design Optimized Least Mean square architecture for adaptive filter Jalaja S., Vijaya Prakash A. M

PDF 1-9

An Area Delay Optimized Carry-Select Adder Sareeka Tulshiram Deore

PDF 10-14

Design, Verification and Circuit Level Implementation of a Ballistic MOSFET Arun Kumar Chatterjee, B. Prasad

PDF 15-22

Performance Analysis of CMOS and FinFET Based SRAM Jeny Elsa Joji, Sreekala K. S., Dhanusha P. B.

PDF 23-27

Design and Analysis of MAC Unit Using Single Precision Floating Point Vedic Multiplier Athira A D, Anjaly Krishnan

PDF 28-35

A Time Domain Analysis on Chip High Speed VLSI Optical Interconnection Network Abhishek Sharma, Sudhir Kumar Sharma

PDF 36-44

A Dual Material Control Gate Tunnel Field Effect Transistor for an Asymmetric Doping at Source and Drain Regions Pratiksha Kharat

PDF 45-53