Journal of VLSI Design Tools & Technology (JoVDTT)

Vol 6, No 3 (2016)

Open Access  Subscription or Fee Access

Table of Contents

Articles

Area Efficient Layout Design of Two Bit Magnitude Comparator Using Novel Strategy shashank gautam, pramod sharma

PDF 1-6

Design of Booth Encoded Multi-Modulus {2n-1, 2n, 2n+1} RNS Multiplier saguna goel, sakshi bajaj, amanpreet kaur

PDF 7-14

Design of FPGA Based ALU Using Reversible Logic Gates vishal A Wankhede, ramprasad M gawande

PDF 15-21

Linearity Analysis of Traditional Single and Double Balanced Down Conversion Mixers akash I mewan, N M Devashrayee

PDF 22-27

Development of System for Speech Enhancement using Combinational Adaptive LMS on Reconfigurable Platform pradeep C bhaskar, prachi S gosavi

PDF 28-34

Design of High-Speed and Low-Power Carry Skip Adder gutlapalli venkatrao, motkuri krishna

PDF 35-44

A Unified Ultra-Low Power Architecture of Probabilistic Adder Based on GDI Technique B S Patro, srinibasa padhy, monica swain, J K Das

PDF 45-55

Survey of System-on-Chip Modular Test Approach harpreet vohra, amardeep singh

PDF 56-70

Design of Low Power Resistor Less Flash ADC for UWB Receiver Applications ankush chunn, rakesh kumar sareen

PDF 71-87

VHDL Implementation of Network-on-Chip Router using Round Robin Arbiter minakshi m wanjari, pankaj agrawal, ravindra kashirsagar

PDF 88-93

eISSN: 2249–474X