Journal of VLSI Design Tools & Technology (JoVDTT)

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Home > Archives > Vol 7, No 1 (2017)

Table of Contents

Articles

Implementation of Carry Select Adder with Reduced Area Scheme pinaki satpathy

PDF 1-5

A Novel Approach for 3D Floor Planning in VLSI with Minimum Dead Space using a New Topological Structure ajoy kumar khan

PDF 6-17

Comparative Analysis of Phase Frequency Detector for Phase-Locked Loops Gunjankumar R Modi, Priyesh P Gandhi, Nilesh D Patel

PDF 18-28

Low-Power Design of Content Addressable Memory using Master Slave Match Line Architecture boda venkata lakshmi, Boggavarapu satish kumar

PDF 29-34

Analysis and Implementation of Folding and Interpolating Analog to Digital Converter using Submicron CMOS Technology rahulkumar S suthar, priyesh P gandhi

PDF 35-40

A Novel Approach Based On-Chip High Speed Optical Interconnection Network abhishek sharma, sudhir kumar sharma, pramod sharma

PDF 41-48

Enhancement in RMPA Parameters using Slotted Rhombus Connected Square Shaped Antenna with Left Handed Metamaterial ram kishor sharma, mahendra kumar pandey, sandeep kumar agrawal

PDF 49-54