Journal of VLSI Design Tools & Technology (JoVDTT)

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Home > Archives > Vol 9, No 1 (2019)

Vol 9, No 1 (2019)

Open Access Open Access  Restricted Access Subscription or Fee Access

Table of Contents

Articles

Implementation and Analysis of 32-bit pipelined RISC Processor Architecture
P. Indira, M. Kamaraju
PDF Restricted Access
1-14
Design of Active Filter using CMOS based IInd Generation Current Conveyor in Current Mode
Vandana Khanna, Srishti Singhal, Sushant Nagpal
PDF Restricted Access
15-21
Design of Slew Aware Clock Distribution Network for Ultra Low Power Sub-threshold Applications
Rupali Ashok Walunj, Sachin Dattatraya Pable, Gajanan Kashiram Kharate
PDF Restricted Access
22-37
Implementation of Different Low Power Techniques on CMOS Inverter and NAND Circuits
Karishma Yadav, Vandana Khanna, Gaurav Shingwani, Ishita Ishita
PDF Restricted Access
38-43
Near Field Wireless Powering of Implantable Devices
Simi P Thomas, Aparna Jose
PDF Restricted Access
44-50
Reusable FM0/Manchester Encoding Using QCA
Harshada Dayanand Malage, Usha Jadhav
PDF Restricted Access
51-59


eISSN: 2249–474X