Journal of VLSI Design Tools & Technology (JoVDTT)

• Home
• About
• Login
• Register
• Search
• Current
• Archives
• Announcements
• Editorial Team
• Indexing
• Author Guidelines
• Copyright Licensing Form
• Publication Ethics and Malpractice Statement
• Referencing Pattern
• Manuscript Withdrawal Policy

Home > Archives > Vol 9, No 1 (2019)

Table of Contents

Articles

Implementation and Analysis of 32-bit pipelined RISC Processor Architecture P. Indira, M. Kamaraju

PDF 1-14

Design of Active Filter using CMOS based IInd Generation Current Conveyor in Current Mode Vandana Khanna, Srishti Singhal, Sushant Nagpal

PDF 15-21

Design of Slew Aware Clock Distribution Network for Ultra Low Power Sub-threshold Applications Rupali Ashok Walunj, Sachin Dattatraya Pable, Gajanan Kashiram Kharate

PDF 22-37

Implementation of Different Low Power Techniques on CMOS Inverter and NAND Circuits Karishma Yadav, Vandana Khanna, Gaurav Shingwani, Ishita Ishita

PDF 38-43

Near Field Wireless Powering of Implantable Devices Simi P Thomas, Aparna Jose

PDF 44-50

Reusable FM0/Manchester Encoding Using QCA Harshada Dayanand Malage, Usha Jadhav

PDF 51-59