Vol 5, No 2 (2015)

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Table of Contents

Articles

Design and Analysis of an Efficient Fast Low Power 1 Kb SRAM Cell Using 90nm and 45 nm Microwind Technology
A.K. Pathrikar, Rajkumar S. Deshpande
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1-3
Comparative Analysis of High Speed Comparator for A to D Converters
Priyesh Gandhi, Neha B. Rathod, N. M. Devashrayee
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4-10
Comparative Study of (Operational Transconductance Amplifier) OTA to Design Low Pass Filter
Aakansha Barala, Pooja Sabherwal, Meenakshi Yadav
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11-15
4-Bit Magnitude Comparator Design using Different Logic Styles
Vipul Mittal, Tanushree ., Madhulika Arora, Meenakshi Yadav, Sakshi Chaudhary
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16-22
A Novel Efficient VLSI Architecture for Matrix Multiplication using Compressor-based Multiplier
Kirti Sharma, Anushree .
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23-28
Efficient Analysis and Minimization of Glitches using Threshold Swapped Combinational Clock Gating
J. Sudhakar, A. Mallikarjuna Prasad, Ajit Kumar Panda
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29-37
Review of Design and Implementation of Adder with Increasing Bits by Using Constant Delay Logic Style
Megha Hulkey, Harshvardhan Upadhyay
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38-41
Hardware Optimization of FPGA for I2C Master Protocol and Interfacing with EEPROM Slave
Pragya Sharma, Neeraj Kr. Shukla, Rakhi Nangia
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42-48
Automated Access Backdoor for UVM_REG Layer
Seep Sethi, Neeraj Kr. Shukla
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49-53
Characterization of High Performance Third Generation Current Conveyor using CMOS Technology
Megha M. Patel, Nilesh D. Patel
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54-63
Comparative Analysis of Class-AB Voltage Follower using DTMOS Transistor
Nishtha K. Patel, Nilesh D. Patel
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64-70
Design of 8 Bit High Speed Pipelined ADC
Shivani R. Patel, Priyesh P. Gandhi
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71-80
Tuning Range, Phase Noise and Jitter Analysis of Current Starved Voltage Controlled Oscillator (VCO) for Digital PLL in 45 nm CMOS Technology
Bharat H. Nagpara
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81-89