Journal of VLSI Design Tools & Technology (JoVDTT)

Vol 7, No 2 (2017)

Open Access  Subscription or Fee Access

Table of Contents

Articles

Implementation of RSA and CRT-RSA with MIST to Resist Power Analysis Attacks Hridoy Jyoti Mahanta, ajoy kumar khan

PDF 1-12

Effect of Various Parameters on Threshold Voltage of Virtually Fabricated Lightly Doped PMOS Device nitin sachdeva, munish vashishath, P K bansal

PDF 13-20

Low-Offset High Speed CMOS Voltage Comparator using 180 nm Technology Rohitkumar M. Joshi, priyesh p gandhi

PDF 21-27

Performance Analysis of 3T DRAM Using FinFET Based with Leakage Reduction Techniques at 45 nm Technology Bharat Tripathi, saurabh khandelwal

PDF 28-34

Low Power High Speed Eight-Transistor (8T) SRAM Cell with Enhanced Data Stability P. Raikwal, V Neema, A Verma

PDF 35-44

High Speed and Low Area Energy Efficient FPGA Implementation using RSD based Elliptic Curve Cryptography Abhay Arvind Koparde, K. Sujatha

PDF 45-50

Carbon Nanotube Transistor Based Novel Ring Oscillator with Minimum Power Consumption at 32 nm Technology Node Nikhil Saxena, chandramoham K, Sapna Navre, Sonal Soni

PDF 51-54

Single Bit Low-Power High-Speed Full Adder Sachin Pandurang Gaikwad, Sujatha kondakinda, Harsh Upadhyay

PDF 55-60

eISSN: 2249–474X