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Issue Title
 
Vol 6, No 3 (2016) A Unified Ultra-Low Power Architecture of Probabilistic Adder Based on GDI Technique Abstract
B S Patro, srinibasa padhy, monica swain, J K Das
 
Vol 5, No 3 (2015) All-Digital Phase Locked Loop (ADPLL) as an Intellectual Property (IP) Core for an Application-specified Integrated Circuit (ASIC) Product: A Survey Abstract
Rajesh Yadav, Neeraj Kumar Shukla, Rajesh Gupta
 
Vol 8, No 3 (2018) An Area Delay Optimized Carry-Select Adder Abstract
Sareeka Tulshiram Deore
 
Vol 1, No 1-2-3 (2011) An Explicit Approach to Compare Crosstalk Noise and Delay in VLSI RLC Interconnect Modeled with Skin Effect with Step and Ramp Input Abstract
shilpi lavania, sunil kumar sharma
 
Vol 2, No 1-2-3 (2012) An FPGA-based Controller Design for Servo Actuator Using Xilinx System Generator and HDL Cosimulator Abstract
T. ananthan, M V Vaidyan, M V Varghese
 
Vol 2, No 1-2-3 (2012) An Innovative Approach of the Analysis of the Low Noise of a CMOS-Based Amplifier for Analog Signal-based Applications Abstract
rajinder tiwari, R. K. Singh
 
Vol 6, No 2 (2016) Analysis and Characterization of Different Topologies of Dynamic Latch based CMOS Comparators for Delay, Offset and Power Abstract
Vijay Savani, N M Devashrayee
 
Vol 7, No 1 (2017) Analysis and Implementation of Folding and Interpolating Analog to Digital Converter using Submicron CMOS Technology Abstract
rahulkumar S suthar, priyesh P gandhi
 
Vol 1, No 1-2-3 (2011) Analysis of Resource Utilization for a Floating-Point Complex Multiplication in FPGA Abstract
anitha Mary
 
Vol 1, No 1-2-3 (2011) Analysis of VLSI Circuits Designed with Single and Dual Channel Strained Silicon MOSFETs in Nanoregime Abstract
neha sharan, ashwani rana
 
Vol 8, No 2 (2018) Area and Power Improvement with New Initial Ordering Method Combined with Sift Algorithm for BDD Mapped Circuits Abstract
M. Balal Siddiqui, M. T. Beg, S. Naseem Ahmad
 
Vol 6, No 3 (2016) Area Efficient Layout Design of Two Bit Magnitude Comparator Using Novel Strategy Abstract
shashank gautam, pramod sharma
 
Vol 5, No 2 (2015) Automated Access Backdoor for UVM_REG Layer Abstract
Seep Sethi, Neeraj Kr. Shukla
 
Vol 1, No 1-2-3 (2011) Automatic Switch cum Fuse IC for Low Voltage, Low Power, High Performance Current Conveyors Abstract
ashutosh tripathi
 
Vol 8, No 1 (2018) AXI Bridge and DMA/Bridge Subsystem for PCIe Abstract
Shivani Malhotra, Neelam Rup Prakash
 
Vol 7, No 3 (2017) Carbon Nanotube Transistor Based Novel Ring Oscillator with Minimum Power Consumption at 32 nm Technology Node Abstract   PDF
Chandramohan K, Nikhil Saxena, Sapna Navre, Sonal Soni
 
Vol 7, No 2 (2017) Carbon Nanotube Transistor Based Novel Ring Oscillator with Minimum Power Consumption at 32 nm Technology Node Abstract
Nikhil Saxena, chandramoham K, Sapna Navre, Sonal Soni
 
Vol 6, No 2 (2016) Challenges Beyond 100 nm MOS Devices Abstract
savita maurya, sarita Shrivastava
 
Vol 5, No 2 (2015) Characterization of High Performance Third Generation Current Conveyor using CMOS Technology Abstract
Megha M. Patel, Nilesh D. Patel
 
Vol 5, No 1 (2015) Characterization of High Speed Phase Frequency Detector Circuit Abstract
Nilesh D. Patel, Amisha P. Naik
 
Vol 8, No 2 (2018) Characterization of Low Power-Low Jitter Digital PLL Abstract
Nilesh D. Patel, Amisha P. Naik
 
Vol 8, No 3 (2018) Circular Retiming technique to design Optimized Least Mean square architecture for adaptive filter Abstract
Jalaja S., Vijaya Prakash A. M
 
Vol 6, No 1 (2016) Cluster Based Sleep Transistor Approach for Low Power 6T SRAM Cell Abstract
P. Raikwal, V. Neema, A. Verma
 
Vol 5, No 3 (2015) CMOS Gm-C IF Filter using SCA for Dual Band Receiver Abstract
Kehul A. Shah, NM Devashrayee
 
Vol 3, No 2 (2013) Cogeneration of Fast Motion Estimation Processor and Algorithms Using Loss Less Compression Abstract
M. Viji, S. Chitra
 
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