|
Issue |
Title |
|
Vol 12, No 1 (2022) |
Comparison of RSA and ECC Public key Cryptography Techniques in WSN |
Abstract
|
S. Aruna Deepthi, E. Sreenivasa Rao, Pavan Kumar |
|
Vol 2, No 1-2-3 (2012) |
Decimator Design for Sigma-Delta ADC |
Abstract
PDF
|
Narendra Bahadur Singh, tripti sharma, prashant singh |
|
Vol 2, No 1-2-3 (2012) |
Delay Minimization of 3 Cascaded Inverters with the Help of Logical Effort and Transistor Sizing |
Abstract
PDF
|
sampath kumar, neerja singh |
|
Vol 13, No 2 (2023) |
Delta Sigma Fractional N Frequency Synthesis |
Abstract
|
Md. Abdul Muqueem, Dr. V. Raju Reddy, A. Nikitha, R. Sandeepsai, D. Maniteja, K. Naresh |
|
Vol 5, No 2 (2015) |
Design and Analysis of an Efficient Fast Low Power 1 Kb SRAM Cell Using 90nm and 45 nm Microwind Technology |
Abstract
|
A.K. Pathrikar, Rajkumar S. Deshpande |
|
Vol 4, No 2 (2014) |
Design and Analysis of Energy-Efficient GDI Cell and Its Impact on Multipliers |
Abstract
|
preethi rangaraj, naveen raman |
|
Vol 8, No 3 (2018) |
Design and Analysis of MAC Unit Using Single Precision Floating Point Vedic Multiplier |
Abstract
|
Athira A D, Anjaly Krishnan |
|
Vol 3, No 3 (2013) |
Design and Analysis of Source Current Effect on Preamplifier-Positive Feedback-based CMOS Comparator Using 90 nm Technology |
Abstract
|
Vijay Savani, NM Devashrayee |
|
Vol 4, No 1 (2014) |
Design and Implementation of 2nd Order Gm-C IF Tuning Filter Operating at 900 MHz and 88–108 MHz Wireless System for Multi Standard Receiver |
Abstract
|
Kehul A. Shah, N M Devashrayee |
|
Vol 5, No 3 (2015) |
Design and Implementation of an Efficient Ternary Control Unit |
Abstract
|
Satish S. Narkhede, BS Chaudhari, GK Kharate |
|
Vol 13, No 2 (2023) |
Design and Implementation of Carry Select Adder based On Wallace tree Multiplier using Adiabatic Logic |
Abstract
|
K. Madhava Rao, T. Nikitha, S. Shyam Sundar, Sarapu Nithish Chary, M. Rohith Kumar Reddy |
|
Vol 4, No 3 (2014) |
Design and Implementation of Low Noise Amplifier using 90 nm MOS Technology for Bluetooth |
Abstract
|
akash mecwan, nikunj marodiya, vimal zalariya |
|
Vol 6, No 2 (2016) |
Design and Implementation of Low Power 8-bit Level Crossing ADC |
Abstract
|
vaishali gupta, anil kumar gupta |
|
Vol 5, No 3 (2015) |
Design and Performance Analysis of Multi-Standard CMOS LNA Using Switched Capacitor and MIM Capacitor in 180nm Technology |
Abstract
|
Nishant Poras, Priyanka Goyal |
|
Vol 6, No 2 (2016) |
Design and Performance Trends of Low Power Sigma-Delta A/D Converters |
Abstract
|
saima bashir, suhaib ahmed, vipan kakkar |
|
Vol 6, No 2 (2016) |
Design and RTL Implementation for AHB-APB Bridge on SoC |
Abstract
|
shipra sharma, rakhi nangia, neeraj kumar shukla |
|
Vol 11, No 3 (2021) |
Design and Simulation of 4-bit Multiplier using Carry Look-Ahead Adder at Transistor Level |
Abstract
|
Charan Ukku, Dhanunjaya Karumanchi, Venkatachalam K. |
|
Vol 10, No 3 (2020) |
Design, Implementation and Comparative Analysis of Different 8-Bit Multipliers Based on Power, Delay and Hardware Utilization |
Abstract
|
Vandana Khanna, Karishma Yadav |
|
Vol 2, No 1-2-3 (2012) |
Design of 16-bit Pipelined RISC Processor |
Abstract
PDF
|
kalyan acharjya, N B Singh |
|
Vol 5, No 2 (2015) |
Design of 8 Bit High Speed Pipelined ADC |
Abstract
|
Shivani R. Patel, Priyesh P. Gandhi |
|
Vol 2, No 1-2-3 (2012) |
Design of a 10-bit Segmented Current-Steering CMOS D/A Converter for High Speed Communication System |
Abstract
PDF
|
Anil K. Saini, sanjay singh |
|
Vol 9, No 1 (2019) |
Design of Active Filter using CMOS based IInd Generation Current Conveyor in Current Mode |
Abstract
|
Vandana Khanna, Srishti Singhal, Sushant Nagpal |
|
Vol 6, No 3 (2016) |
Design of Booth Encoded Multi-Modulus {2n-1, 2n, 2n+1} RNS Multiplier |
Abstract
|
saguna goel, sakshi bajaj, amanpreet kaur |
|
Vol 2, No 1-2-3 (2012) |
Design of CMOS AM Modem for Wireless Sensors |
Abstract
PDF
|
Shipra Suman |
|
Vol 11, No 3 (2021) |
Design of Decoder Using Domino Logic Circuit for VLSI |
Abstract
|
K Rama Krishna Reddy, Sai Teja Ankuru, Divya Pillutla, Varthya Shirisha |
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