Browse Title Index


 
Issue Title
 
Vol 8, No 3 (2018) Performance Analysis of CMOS and FinFET Based SRAM Abstract
Jeny Elsa Joji, Sreekala K. S., Dhanusha P. B.
 
Vol 9, No 2 (2019) Performance Analysis of DNA Sequencing Using Smith-Waterman Algorithm on FPGA Abstract   PDF
Anna Hakim, Anam Kashtwari, Rajinder Tiwari, Jamini Sharma
 
Vol 2, No 1-2-3 (2012) Performance Analysis of Fe/SiO2/Fe MTJ and Ni/Al2O3/Ni MTJ-based Magnetoresistive Random Access Memories (MRAMs) Abstract
mayank chakraverty, P Arun Kumar, Harish M Kittur
 
Vol 4, No 2 (2014) Performance Estimation of VLSI Design Abstract
Pritam Bhattacharjee
 
Vol 5, No 1 (2015) Power Analysis Comparison of Gated Diode Dram Cell Design on 32 nm Technology Abstract
Prateek Asthana, Sangeeta Mangesh
 
Vol 1, No 1-2-3 (2011) Power Estimation for VLSI Circuits Using Neural Networks Abstract
B Srinath
 
Vol 2, No 1-2-3 (2012) Power Reduction at 90 nm through Circuit Level Modification Abstract
Angshuman Chakraborty, sambhu nath pradhan
 
Vol 3, No 3 (2013) Power-delay Product Optimal Design of Sequential Circuits Using Carbon Nanotubes Abstract
Mahesh Soni, Vineet Sahula
 
Vol 10, No 1 (2020) Privacy Preserving Cloud Data Access using Control and Automation Technique Abstract
Sachin kumar
 
Vol 5, No 1 (2015) Real Time FPGA-based Embedded Architecture of Audio Compression and Decompression Core for Multimedia System Abstract
Moumita Acharya, Shreedeep Gangopadhyay
 
Vol 3, No 1 (2013) Reconfiguring CMOS Driver and Receiver Pair as Pseudo NMOS for Low-swing Signaling On-chip Interconnects Abstract
Balaji B. S.
 
Vol 3, No 1 (2013) Reducing Crosstalk in Arithmetic and Logic Unit Part of a Processor Abstract
Mujeeb Ulla Jeelani, Venkatesh Kumar N., Anoop S. Shandilya
 
Vol 9, No 1 (2019) Reusable FM0/Manchester Encoding Using QCA Abstract
Harshada Dayanand Malage, Usha Jadhav
 
Vol 6, No 2 (2016) Reusable Verification Framework of AMBA AHB-Lite Protocol using HDVL and UVM Abstract
ashima gandhi, neeraj kr. shukla
 
Vol 5, No 2 (2015) Review of Design and Implementation of Adder with Increasing Bits by Using Constant Delay Logic Style Abstract
Megha Hulkey, Harshvardhan Upadhyay
 
Vol 6, No 1 (2016) Review Paper on Static and Dynamic Power Dissipation of Novel CMOS SRAM Cell Abstract
Jitendra Krishna Arya, Ashish Raman
 
Vol 8, No 1 (2018) Review Paper To Design a Low Power CNTFET Based XOR Gate Abstract
Veski Dabas, Surender Kumar Grewal
 
Vol 8, No 1 (2018) Review Paper: Low Power SRAM Cell using FinFET Technology Abstract
Mamta ., Surender Kumar Grewal
 
Vol 10, No 1 (2020) Simulation of Three Section Multilevel Inverter with Reduced Range of Switches Abstract
HARSHIT PANDAY
 
Vol 6, No 1 (2016) Simulation Study of Tapered Shape FinFET Abstract
A. Shrivastava, S. Singh, A. Acharya, G Musalgaonkar
 
Vol 7, No 3 (2017) Single Bit Low-Power High-Speed Full Adder Abstract   PDF
Sachin Pandurang Gaikwad, Sujatha Kondakinda, Harsh Upadhyay
 
Vol 7, No 2 (2017) Single Bit Low-Power High-Speed Full Adder Abstract
Sachin Pandurang Gaikwad, Sujatha kondakinda, Harsh Upadhyay
 
Vol 6, No 3 (2016) Survey of System-on-Chip Modular Test Approach Abstract
harpreet vohra, amardeep singh
 
Vol 6, No 1 (2016) Switched Capacitor-based RC Filter Abstract
jinal A prajapti, Mehul L Patel
 
Vol 10, No 1 (2020) Switching Loss Calculation of Power MOSFET using the Estimation Technique Abstract
Soumya Sen, Souvik Saha, Angshuman Khan, Rajeev Arya
 
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